A4 Write down the Continuous Assignment statement for the logic circuit shown in figure A4: DOD DID Y - גם DSD 81D SOD AA ENED Figure A4 (2.5 marks) A5 What is the value for signal 'Y', given A = 8'b11011101 and B = 8'b10100101, are the inputs to the following Verilog continuous assignment? assign Y = N(A - B); (2.5 marks) A6 What is the Verilog continuous assignment statement corresponding to the logic circuit shown in figure A6? KD Figure A6 (2.5 marks)
A1 Write down the Verilog-HDL continuous assignment statement corresponding to the circuit of figure A1: (2.5 marks) OEB1D OEB2 D -DO Figure A1 A2 What is the logic symbol corresponding to the following Verilog-HDL module? module A2 (input L, M, N, output P); assign PE-LI-MI-N; endmodule (2.5 marks) A3 Write down a Verilog-HDL primitive gate instance corresponding to the waveforms shown in figure A3, assuming A and B are inputs and F is the output? B 00 F F Time inns 15 0 520 55 50 80 75 Figure A3 (2.5 marks)
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