- 4 Build And Simulate In Multisim The State Machine In 3 You Can Start With The Incomplete Circuit In Figure 9 Where 1 (95.09 KiB) Viewed 36 times
4. Build and simulate in Multisim the state machine in (3). You can start with the incomplete circuit in Figure 9 where the circuit diagram of the state equation S3(t + 1) is already wired. You can use 4- input and 3-input AND gates like 74LS21N and 74LS11N, respectively. They can be found under TTL -> 74LS. Use 7432 for OR gates and 7404 for NOT gates (both are also under TTL -> 74LS). Connect a clock (under SOURCES -> DIGITAL_CLOCK) to pin 11 of the 74LS374N (under TTL->74LS_IC) and set the clock frequency to 50Hz. Take a screenshot of your circuit. U10B VCC 5.0V U12A U1 uЗА 74LS21N sz Voe20 S3 U10A 74LS32N 1D 20 30 40 50 RICH 74504D S2 10 20 30 IS 40 50 FE 60 70 U3B תר sk 00 74LS21N d-oc CLK 74504D U3C UND S1 74LS374N GND ? 74504D U3D so So U22 74504D 50Hz Figure 9. Incomplete circuit of the state machine 5. Use a logic analyzer to view the state outputs S0, S1, S2, and S3. Set the logic analyzers sampling rate to 100 Hz and 'Clocks/Div' to 2. Run the simulation and take screenshots of your simulation. Did your circuit run as expected?