VHDL Modeling and Testbench The circuit below shows a 4 bit adder-subtractor. A3 B3 A2 B2 A1 B1 Ao Bo 10/ 1 0, C4 \1 0,

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Vhdl Modeling And Testbench The Circuit Below Shows A 4 Bit Adder Subtractor A3 B3 A2 B2 A1 B1 Ao Bo 10 1 0 C4 1 0 1 (18.97 KiB) Viewed 46 times

Create a simulation Testbench to
verify your design above. Your testbench should report by
using ASSERT, with a severity
of WARNING should the output be
incorrect.
You may choose any 4 sets of 2x4-bit number as stimulus
for your testbench. 2 sets for addition operation and the other 2
for subtraction.
VHDL Modeling and Testbench The circuit below shows a 4 bit adder-subtractor. A3 B3 A2 B2 A1 B1 Ao Bo 10/ 1 0, C4 \1 0, 1-bit Full Adder S3 C3 1-bit Full Adder S2 C2 1-bit Full Adder S1 C1 \10/ 1-bit Full Adder So Co D