Devise the transistor-level circuit diagram of a single 4-input CMOS logic gate to implement the following logic functio

[correctanswer]

Devise the transistor-level circuit diagram of a single 4-input
CMOS logic gate to implement the following logic function:
̅̅̅̅ 𝐎𝐏=𝐀∙𝐁 ∙(𝐂+𝐃)
where A, B, C and D are the logic gate inputs and O/P is the
logic gate output. Note: You need to provide a brief explanation of
the approach you have
followed to design the circuit diagram.
(b) Design a stick diagram of the logic gate from (a),
using dual-well, CMOS technology. Include wells, well taps, contact
cuts, routing of power and GND. Use colour coding and/or detailed
annotations to represent the wires in the different layers.
(c) The logic gate from (a) needs to drive a capacitive
load of 50 fF with a rise- time and fall-time of 0.5 ns. If the
length of all transistors is 0.2 μm, calculate the required widths
for all P-type and all N-type MOSFETs in your logic gate to achieve
the required edge-speeds. Clearly show the calculation steps of
your solution.
Assume VDD = 5 V, K’n = 50 μA/V2, K’p = 20 μA/V2