Problem 4: Consider the combinatorial logic circuit below that is evaluated for static timing analysis (STA). Gates are

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Problem 4 Consider The Combinatorial Logic Circuit Below That Is Evaluated For Static Timing Analysis Sta Gates Are 1 (129.24 KiB) Viewed 27 times

Problem 4: Consider the combinatorial logic circuit below that is evaluated for static timing analysis (STA). Gates are replaced with blue boxes specifying the propagation delay. Signal arrival times are given as AT:x where x is the time the signal arrives. Assume the circuit is operated at 10GHz. Answer the 4 questions below. (2 Points each) AT:5 30ps AT:0 20ps 10ps 25ps AT:10 AT:0 25ps 1.) What is the maximal arrival time of the circuit in picoseconds? 2.) What is the minimal arrival time of the circuit in picoseconds? 3.) What is the maximum setup time that the Flip Flop registering the signal needs to satisfy to enable correct operation? Your answer should be rounded to one place after the decimal point. 4.) What is the maximum hold time that the Flip Flop registering the signal needs to satisfy to enable correct operation? Your answer should be rounded to one place after the decimal point. AT:5