Design an IC of 4-1 Multiplexer by carefully observing the following constraints. i. Use 2-input gates, 2-1 Mux only. i

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Design an IC of 4-1 Multiplexer by carefully observing the following constraints.
i. Use 2-input gates, 2-1 Mux only. ii. Maximum delay of a 2-1 Mux shall be less than 11 τ.

The required design parameters are as follows:
i. Each 2-1 mux has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. ii. Assume the input probabilities of all inputs as 0.5. iii. You are using a standard cell process with an average switching capacitance of 450 pF/mm2. The chip has an area of 70 mm2 and runs at 450 MHz at VDD = 0.9 V.

You are required to provide the following information in your CEP report.
1. Draw a schematic diagram of the design. 2. Estimate the delay D of 2-1 Mux. 3. Optimize the design for delay using any logic. 4. Draw the circuit diagram of your design with transistor sizes to achieve the calculated delay. 5. Find out the activity factor. 6. Estimate the dynamic power consumption of your chip.