Exercise 1: Giving the declarations below: SIGNAL s1: BIT; SIGNAL S2: BIT_VECTOR (7 DOWNTO 0); SIGNAL $3: STD_LOGIC; SIG

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Exercise 1 Giving The Declarations Below Signal S1 Bit Signal S2 Bit Vector 7 Downto 0 Signal 3 Std Logic Sig 1 (79.91 KiB) Viewed 21 times

Exercise 1: Giving the declarations below: SIGNAL s1: BIT; SIGNAL S2: BIT_VECTOR (7 DOWNTO 0); SIGNAL $3: STD_LOGIC; SIGNAL 84: STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL $5: INTEGER RANGE -35 TO 35; VARIABLE v1: BIT_VECTOR (7 DOWNTO 0); VARIABLE V2: INTEGER RANGE -35 TO 35; What are the legal and illegal Assignments and explain? s2 (7) <= s1; s3 <= 84(0); s2 <= v1 XOR "10001000"; s5 <=v2/2; s1 (0) <= s2(0); s3 <= s1 OR s2 (2); s2 <= (8=> '0', OTHERS=> 'Z'); v2 <= -35; s3 <= '2'; s2 <= (OTHERS=> '0'); v2 := 35; v1 :="11110000"; s3 := 'Z'; s2 ( 7 DOWNTO 5) <= v1 (3 DONWTO 0) OR "1000"; v1 (7) <= s1 AND S2(0); s4 (0) <= s2(0);