Write the synthesizable verilog code for a RAM based FIFO. You are given the sram_fifo toplevel module with its inputs a

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Write The Synthesizable Verilog Code For A Ram Based Fifo You Are Given The Sram Fifo Toplevel Module With Its Inputs A 1 (120.07 KiB) Viewed 32 times

Write the synthesizable verilog code for a RAM based FIFO. You are given the sram_fifo toplevel module with its inputs and outputs. You are also given a dual-ported sram block which has 16 entries, where each entry stores 8 bits. The write_enable (we) signal determines whether a port is used to read or write data in a clock cycle. Use the skeleton below and fill in the brackets to connect the sram block to your design. HINT: Use a ring buffer to store data in the sram, write the logic to maintain information about the head and tail of the ring buffer. Lastly use the information to generate empty/full signals. Assume that (shift_in && full) and (shift_out && empty) never happen (no need to check). (14 Points) module sram_fifo ( input clk, res_n, input shift in, shift_out, input [7:0] data_in, output reg empty, output reg full, output reg [7:0] data_out ); ram_dp_ar_aw 16x8_BIT_DP_RAM ( .address_0 ( //16 entries, 8 bit wide RAM ), // address 0 input. .data_0 ( .we_0 ( ), // data_0 bi-directional ), // write enable input_0 ), // address_1 input. .address_1 ( .data_1 ( ), // data_1 bi-directional .we_1 ), // write enable input_1 );