2 Figure Q2 Shows A 74ls163 An Integrated Circuit 4 Bit Synchronous Binary 15 Counter An Active Low Clear Input Will S 1 (41.04 KiB) Viewed 28 times
2 Figure Q2 Shows A 74ls163 An Integrated Circuit 4 Bit Synchronous Binary 15 Counter An Active Low Clear Input Will S 2 (41.04 KiB) Viewed 28 times
2 Figure Q2 shows a 74LS163, an integrated circuit 4-bit synchronous binary 15 counter. An active-LOW clear input will synchronously reset the counter. ENT and ENP are two enable inputs. Design a divide-by-48 counter using two cascaded 74LS163 counters (one for a modulus-8 counter and the other for a modulus-6 counter). This counter has an output Y which is HIGH only at the maximum count. Do D, D, D, CTR DIV 16. CLR LOAD ENT RCO ENP CLK TC= 15 lo Q Q₂ Q3 Figure Q2
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