separately i.e. adder, MUX, etc. and then instantiate these
components to model the whole ALU.
- A Use Verilog Behavioral Modeling To Model Each Component Separately I E Adder Mux Etc And Then Instantiate These C 1 (91.97 KiB) Viewed 83 times
of the required Multiplexers and adder (I need the modules of all
of the components(Adder/Multiplexers/etc... And the final ALU that
instantiates them))
Please refer to the pictures and answer what is required, don't
copy others' wrong answers.
The ALU should do the functions specified in the pictures.
Arithmetic and Logic Unit (ALU) ALU performs arithmetic and logic functions A[n-1:0] B[n-1:0) n n F[2:0] + ALU 3 * We will design an ALU with 8 functions VC The function F is coded with 3 bits as follows: R [n-1:0] Function ALU Result Function ALU Result R= A + B R = A&B R= A + B + 1 F = 000 (ADD) F = 001 (ADD + 1) F = 010 (SUB - 1) F = 011 (SUB) F = 100 (AND) F = 101 (OR) F = 110 (NOR) F = 111 (XOR) - R= A-B-1 R = AB R = ~( AB) R = (A^B) R=A-B
Arithmetic and Logic Unit (ALU) = A[n-1:0] B[n-1:0] F[2:0] = 3-bit Function code n F1 n XOR n+n n n nt tn n OR n XOR gates n AND gates gates gates n Cn- 1 n-bit Adder cok Fo CA nt n n+ n 0 1 2 mux 37545o = F F. n 2 0 1 V = Overflow C = Carry output mux'st-F2 VC n Result = R[n-1:0]