10. Assume we have 8 registers, RO-R7, and we have a pipeline of 7 stages: Instruction Fetch (IF), Instruction Decode (I

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10 Assume We Have 8 Registers Ro R7 And We Have A Pipeline Of 7 Stages Instruction Fetch If Instruction Decode I 1 (50.59 KiB) Viewed 55 times

10. Assume we have 8 registers, RO-R7, and we have a pipeline of 7 stages: Instruction Fetch (IF), Instruction Decode (ID), Instruction Issuing Queue (IQ), Operands Fetch (OF), Execution (EX), Write Back (WB), and Commitment (CO). Each stage needs exactly 1 cycle to finish its work. Also assume that the pipeline supports forwarding, which means the result of WB can be forwarded to OF. Given the following piece of instructions: 11: R1 = RO + R2 12: R3 = R1 + R4 13: R1 = R5 R6 14: R5 RO + R7 (1) Identify all the data dependencies and their types. (5%) (2) What is the new order of execution if we run the instructions in the 7 stage pipeline that supports forwarding, register renaming, and out-of-order execution? (5%) (3) How many cycles do we need if we run the instructions in the 7 stage pipeline that supports forwarding, register renaming, and out-of-order execution? (5%)