Question 3 Non-volatile Main Memory [35 pts] You are designing an ultra low power processor to be used in a deep space e

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Question 3 Non Volatile Main Memory 35 Pts You Are Designing An Ultra Low Power Processor To Be Used In A Deep Space E 1 (81.5 KiB) Viewed 19 times

Question 3 Non-volatile Main Memory [35 pts] You are designing an ultra low power processor to be used in a deep space exploration mission. Since the power supply in deep space is unreliable and may be cut off at any random time during the trip, you are exploring the use of a new non-volatile memory technology, called memory N, to implement your main memory system. The goal is that even if the power supply is cut off randomly, the processor can immediately resume its operation when power resumes without loosing any data. Memory N has the following characteristics: . Read latency: 1 μs ● Read 1 word (16 bit) at a time, no burst read. • Writes must be performed in the unit of a write region. Each region is 128 words with continuous and aligned addresses. To write data smaller than 1 region, e.g. to write just 1 word, the processor must perform the following 3 steps using a read-update-write method: Write Step 1: Read the entire region from the memory, then Write Step 2: update the necessary data, then Write Step 3: Write the region back to the memory. • Write Step 1 above takes 128 x read latency = 128 μs. • Write Step 3 above takes 512 μs.

Part(a) [6 pts] Your baseline processor A has NO CACHE. It is a single cycle processor operating at a clock frequency of 1 MHz. It has a load-store architecture and has 16-bit words and addresses. It includes a dedicated buffer, called M, to facilitate region-based memory writing. M has the size of one write region and is implemented using standard SRAM technology on the processor chip. All non-memory instructions have CPI= 1. In processor A, all writes are implemented by following all 3 write steps above (read-update-write). Using processor A, what is the CPI of load word (1w) and store word (sw) instructions?

Part (b) [4 pts] Assuming 30% of the instructions of program P are memory operations. Among them, 80% of these memory operations are reads and the rest are writes. What is the average CPI for this program P?

Part(c) [5 pts] You are evaluating a new processor B that is the same as A except there is an additional instruction and data cache. On cache hits, both caches return data in 1 cycle. On cache misses, the cache access memory N the same way as in processor A above. For the benchmark program P, the instruction cache has a miss rate of 7%, and data cache has a miss rate of 19%. 65% of the data cache misses are write misses. What is the average memory access time (AMAT) for (i) the instruction cache and (ii) the data cache?

Part(d) [5 pts] Assume processor A and B runs at the same clock speed. Comparing program P running on processor A and B, which processor is faster and by how much?

Part(e) [10 pts] As an elite ELEC3441 student, you realized that you can improve the performance of memory writes in processor A by reusing the on-chip write buffer M as a cache. Call this Processor C. Assuming you cannot increase the size (capacity) of buffer M, describe how this on-chip storage can be used as a cache by describing the following: 1. What is its cache organization? 2. What is its line size? 3. What is its replacement policy? 4. What is its write policy? 5. Which bits of the address will serve as a tag? 6. What additional hardware are needed to support these cache functions? 7. How will the proposed cache organization improve memory write performance over the original read-update-write method? Note: there can be multiple ways to answering this question. State any assumptions you have made if in doubt.

Part (f) [5 pts] Assuming once you use the write buffer as cache, the miss rate is 63%. Compare to Processor B, (which implemented both an instruction cache and a data cache), which processor is faster when running P and by how much?