Problem 2 (45 pts): One of the key applications of n-bit shift registers is pseudo random number generation (PRNG). The

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Problem 2 (45 pts): One of the key applications of n-bit shift registers is pseudo random number generation (PRNG). The basic structure of a pseudo random number generator is a shift register whose serial input bit is a linear function of some bits of the current shift register content. The bit positions that affect the serial input are called taps. The general form of a pseudo random bit generator is a shift register with two or more flip-flop outputs XOR’ed together and fed back into the first flip-flop. The block diagram of a 3-bit random bit generator is shown below: XOR XOR to х dy tu x jaa da 012 clock dffo dff1 dff2 (a) Circuit (b) Symbol X+X+1
The taps in this example are at bit 0 and bit 2, and can be referenced as [0,2]. All of the register elements share a common clock input, which is omitted from the symbol for reasons of clarity. The data input to the random sequence is generated by XOR-ing the tap bits; the remaining bits function as a standard shift register. The determination of the taps is based on an algebraic polynomial known as primitive polynomial. In the above example, the primitive polynomial is: x +x+1=[1]*x* +[0]* x² +[1]*x +[1]* t° = taps = [101]=OX 6 + The tap for each term in polynomial is set to 1 when the term is present in the polynomial and set to o when the term is missing. The zero taps do not connect to the XOR gate. A 12-th order polynomial for a 12-bit PRNG is given below: .12 11 4 x?? + x + xº +x+ +1=> taps = [111000001000] = OXE08 10 (a) Design an 8-bit PRNG with the following primitive polynomial and draw the schematic circuit: (10 pts). xº +x^ +x+x^ +1 tx x3
(b) Write the Verilog code for the 8-bit PRNG according to the design in step (a). Use the parameter keyword to make the design flexible for the number of bits. Initialize the shift registers content with a non-zero value (hint: set all the shift register values to all 1s). Submit your .v file and compile the code in Quartus and provide screenshots showing your code plus the compilation results. The screenshot should show the compilation results with the source code in the same screenshot. (20 pts) (c) This PRNG has a period of 256, i.e. it generates 256 random bits before it starts repeating the same sequence. Write a type-3 testbench that runs the circuit for 266 (256 + 10) clock cycles (it should finish the first cycle and stops 10 clock cycles into the second period). The first 10 samples of the second period should match the first 10 samples of the first cycle. Verify the output of the simulation by using this logic (in your testbench in ModelSim). Submit your testbench code (.v) and the (.tv) plus the verification results in ModelSim on Canvas. (15 pts)