Project 3 tp a) Sketch a transistor-level schematic and layout for Y ABC + D b) Give the sizes of all transistors, assum

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Project 3 Tp A Sketch A Transistor Level Schematic And Layout For Y Abc D B Give The Sizes Of All Transistors Assum 1 (110.38 KiB) Viewed 23 times

Project 3 tp a) Sketch a transistor-level schematic and layout for Y ABC + D b) Give the sizes of all transistors, assume that for the basic inverter n = 4, 4,Cox= 430 uA/V?, and upCox= 107.5 ”A/V>, and that the channel length is 130 nm, Vpp = 1.2 V, and V tn =-V, = 0.4V. Verify your design with. c) From the OrCAD or LTSPICE, find tphl, tplu, t, and tf (Hint: Compare output (Y) with input (D) assume D = C). d) Use the transistors size in part (b) and draw the circuit in Pseudo nMOS logic. Verify your design with OrCAD or LTSPICE. =