Here is a description of a CPU memory system: •64-bit virtual address; 48-bit physical address. •L1 iTLBs: – 8KB pages:

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Here is a description of a CPU memory system:
•64-bit virtual address; 48-bit physical address.
•L1 iTLBs:
– 8KB pages: 256-entry; 8-way set-associative.
– 2MB pages: 32-entry; 8-way set-associative.
•L1 dTLBs:
– 8KB pages: 64-entry; 8-way set-associative.
– 2MB pages: 32-entry; 4-way set-associative.
– 1GB pages: 8-entry; fully-associative.
•Unified L2 TLBs:
– Combined 8KB / 2MB pages: 1024-entry; 16-way
set-associative.
– 1GB pages: 128-entry; 16-way set-associative.
•L1 I-cache:
– Virtually indexed, physically tagged.
– 8-way set-associative; 64-byte block.
– size = maximum possible size without creating aliases.
•L1 D-cache:
– Virtually indexed, physically tagged.
– 8-way set-associative; 32-byte block.
– size = maximum possible size without creating aliases.
•Unified L2 cache:
– 256 KB of data (excluding tag bits).
– 4-way set-associative; 128-byte block.
•Unified L3 cache:
– 2 MB of data (excluding tag bits).
– 8-way set-associative; 256-byte block.
Exercise 1 (24 points)
For the subsequent questions, list the number of tag bits and data
bits per TLB/cache entry, and the total number of bytes in
TLB/cache. You only need to consider tag and data bits; ignore any
status bit.
a) (2 points) L1 iTLB for 8KB pages.
b) (2 points) L1 iTLB for 2MB pages.
c) (2 points) L1 dTLB for 8KB pages.
d) (2 points) L1 dTLB for 2MB pages.
e) (2 points) L1 dTLB for 1GB pages.
f) (2 points) Unified L2 TLB for combined 8KB / 2MB pages.
g) (2 points) Unified L2 TLB for 1GB pages.
h) (3 points) L1 I-cache.
i) (3 points) L1 D-cache.
j) (2 points) Unified L2 cache.
k) (2 points) Unified L3 cache.