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Implement the CPU shown in Figure 1 using Verilog, the CPU must be implemented using structural models only and should meet the following requirements: Register File Reg A Reg B Reg C Reg D Op1 Op2 Op3 Op4 Op1 Sel Op2 Sel N Operation 2 5 ah Op3 Sel Op4 Sel ALU N NY ILM Clk 2 Result Status Figure 1. CPU model • The CPU consists of an ALU, a register file, a clock, a status, and Result registers. • There is a 5-bit control line named Operation. Operation is responsible for selecting the operation to be performed by the ALU • The register file consists of four 8-bit registers (A, B, C, D). Assume values stored in the registers are unsigned.
The ALU has four 8-bit input Ports (Op1, Op2, Op3 and Op4). Op1, Op2, Op3 and Op4 values are fetched from the registers (A, B, C and D) based on Op1 Sel, Op2 Sel, Op3 Sel and Op4 Sel control lines as shown in Table 1. Table 1. Register Select Operand Selection Selected Register 00 01 с 10 11 • The ALU has two output registers: result and status. Result is a 12-bit register while status is a 3- bit register. • At the negative edge of the clock, the ALU reads the selected registers and performs the required operation (By updating the result and the status registers) • The operations being performed in the ALU are based on table 2. Table2. Operations in the ALU. Operation ALU operation Result register Register affected bits Status
Operation Table2. Operations in the ALU. ALU operation Result register Status Register affected bits z Z Z 00000 00001 00010 00011 00100 00101 00110 00111 NAND--Bitwise Operation NOR--Bitwise Operation XOR -- Bitwise Operation Circular Shift Right for Op4 Circular Shift Left for Op4 One's complement for Op3 Two's complement for Op3 Logical AND Z 01000 Logical OR z 01001 Comparator (Op1&Op4) (Op1-10p4) (Opi Op4) Op4 circular shifted Right Op4 circular shifted Left One's complement for Op3 Two's complement for Op3 1 if (Opi l= 0 AND Op2 t= 0) 0 Otherwise 1 if (Opi != 0 OR OP2 != 0) o Otherwise O {if Op2 > Op4) 1 {if Op2 = Op4) 2 {if Op2 <Op4) {Op4[2:01. Op2[2:01,Op3[1:0}} Opl + Op3 Opl - Op3 BCD representation of Op2 Ex: if Op2 = (1110 0011) Then result (0010 0010 0111) aco BCD representation of Op3 Ex: if Op3 = (1110 0011) Then result (0010 0010 0111).CO Z Z. C.V 01010 01011 01100 01101 Concatenate Binary Addition Binary Subtraction Binary to BCD Conversion-1 ZV 01110 Binary to BCD Conversion-2 01111 BCD Addition 2.C Covert the numbers in Op2 and Op3 to BCD then perform Op2 + Op3 10000 BCD Subtraction Ex: Op2 after conversion to BCD = (0011 0101) ncp = 35 Op3 after conversion to BCD - (0010 0110) eco =26 Result = (0000 0110 0001) aco=61 Covert the numbers in Op2 and Op3 to BCD then perform Op2 - Op3 Ex: Op2 after conversion to BCD (0011 0101) CD=035 Op3 after conversion to BCD (0010 0110) c =26 Result = (0000 0000 1001) eco = 009 2.V ZV BCD
The status register has three bits/flags. See Table 3. C= 1 when an addition operation produces carry, and O by default. 2 = 1 when the result register equals to zero, and O by default. V=1 when an addition or subtraction operation produces an overflow. Table 3. Status Register Bits Bit 0 Bit 2 с Bit 1 Z V