Pick Problem 2 or 3 (Do not do both) 2. (40 points) Given the following Verilog HDL of a combinational logic circuit: EC

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Pick Problem 2 Or 3 Do Not Do Both 2 40 Points Given The Following Verilog Hdl Of A Combinational Logic Circuit Ec 1 (65.81 KiB) Viewed 25 times

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Pick Problem 2 or 3 (Do not do both) 2. (40 points) Given the following Verilog HDL of a combinational logic circuit: ECE 2300 - Digital Logic Design A. Gonales module funct input A, B, C, output Y wire F0, F1; not (F0, C); and (F1, B, FO); or (Y, F1, A); endmodule (a) Draw the logic diagram. (b) Find the "Sum-of-Minterms" form, and re-write the module as a User-Defined Primitive (UDP), (c) Re-write the module so it uses Behavioral Modeling. (d) Write a simple test bench that instantiates the original module and generetes all 8 input combi- nations using the repeat statement. Print the results to console.