1 Pipeline: A particular (fictional) CPU has the following internal units and timings (WR and RR are write/read register

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1 Pipeline A Particular Fictional Cpu Has The Following Internal Units And Timings Wr And Rr Are Write Read Register 1 (124.13 KiB) Viewed 46 times

1 Pipeline: A particular (fictional) CPU has the following internal units and timings (WR and RR are write/read registers, ALU does all logic and integer operations and there is a separate floating point unit FPU. Timings for each unit in picoseconds are: IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380 (assume instruction read and memory access are average time for access to cache) There are 5 basic instruction types: - here are instruction sequence for each type, time in picoseconds and percentage of each type in a typical set of test codes: 1. LOAD : IR+RR+ALU+MEM+WR : 780, 20% 2. STORE: IR+RR+ALU+MEM : 730, 10% 3. LOGIC/INTEGER: IR+RR+ALU+WR: 520, 40% 4. FLOATING POINT: IR+RR+FPU+WR : 700, 10% 5. BRANCH: IR+RR+ALU : 270, 20% 1 cycle is 780ps = .780 nanoseconds for this machine, on the assumption that all instructions take 1 cycle (assume all memory access is in cache). Clock frequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1 1.1 Outline what a pipeline would look like: Give: . number of stages • operations in each stage • new cycle time and frequency 1