Simplified Cla Adder Sc Simplified Multiplexer D Set Q D Set Q D Setq Clr Clr Clro Parallel Load Register Clk Reset Z2 Z 1 (224.74 KiB) Viewed 65 times
Simplified CLA adder SC Simplified Multiplexer D SET Q D SET Q D SETQ CLR CLR CLRO Parallel Load Register clk reset z2 z1 zo FIGURE 5.32 A synchronously cleared bit-parallel mod-8 up-counter using a simplified CLA adder and a simplified MUX.
Problem I: Consider the sequential circuit in Figure 5.31 where the adder is a CLA. Its simplified circuit is shown in Figure 5.32. Assuming that the Flip-Flips register set-up time, clock-to-q, and clock-skew are each 0.1 ns, AND gate = 0.2 ns and EXOR = 0.3 ns determine the upper bound for its clock frequency. (5 pts)
Join a community of subject matter experts. Register for FREE to view solutions, replies, and use search function. Request answer by replying!