- Question 23 5 Pts Some Portion Of Cache System A Represented Below The System Is Byte Addressable And The Block Size Is 1 (65.94 KiB) Viewed 38 times
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Question 23 5 pts Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag Line Number Word within block oo 01 10 11 10 1000 0100 10010110 1101 201061161162116 10 1000 0100 10010110 1110 32167216 C216D216 10 1000 0100 10010110 1111 421082164116 A216 10 1000 0100 11010111 0000 E21092165216 B216 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 3. If CPU requests to read memory address A1 25 BA, what data does CPU receive? 4. If CPU requests to read memory address A1 35 C2, what data does CPU receive? 5. If we access memory as the following order in cache system A: A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 how many cache misses would occur for the data request?
Question 24 Some portion of cache system B represented a 2-way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag Set Number Word within block bo 01 10 11 10 1000 0100 10010110 1101 201661161162116 11 1100 0100 10010110 1101 32167216 6216 P216 10 1000 0100 10010110 1110 142168216 4116 A216 11 1100 0100 11010110 1110 5216 9216 216 B216 10 1000 0100 10010110 1111 20160116 01165116 11 1100 0100 10010110 1111 $2167216216 P216 10 1000 0100 10010111 0000 4216 8216 6116 1216 11 1100 0100 11010111 0000 5216 42165216 B216 10 1000 0100 10010111 0001716611661162116 11 1100 0100 10010111 0001 32167216C216 0216 10 1000 0100 10010111 0010 12168216 4116 4216 11 1100 010011010111 0010 52169216 5216 B216 1. What is the size of the main memory for cache system B? 2. What is the size of cache memory? 3. If we request memory read from memory address F1 35 C3. what data do we read? 4. If we request memory read from memory address A1 25 BA, what data do we read? 5. If we access memory as the following order in cache system B: A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF 38 B1 FF B8 how many cache miss(es) would occur for the data request?