Consider VHDL model of an FSM given in the following: library ieee; use ieee.std_logic_1164.all; entity Unknown is port[

[answerhappygod]

Consider Vhdl Model Of An Fsm Given In The Following Library Ieee Use Ieee Std Logic 1164 All Entity Unknown Is Port 1 (46.01 KiB) Viewed 70 times

what gives it away? please draw state diagram and explain..
Modify your code to force the synthesis tool to encode your FSM
states in one hot code. Show only the addition to the given code
and what needs to change. You do not have to write the complete
code.
What does this FSM do?
I'm having issues understanding this topic... I will upvote

Consider VHDL model of an FSM given in the following: library ieee; use ieee.std_logic_1164.all; entity Unknown is port[clk, reset : in std_logic; fsm_in : in std_logic; fsm_out : out std_logic); end Unknown; architecture arch of Unknown is type state_type is (zero, one); signal state_reg, state_next : state_type; begin process (clk, reset) begin if (reset = '1') then state_reg <= zero; elsif (clk'event and clk = '1') then state_reg <= state_next; else null; end if; end process; process(state_reg, fsm_in) begin state_next <= state_reg; fsm_out <= '0'; case state_reg is when zero => if fsm_in = '1' then state_next <= one; fsm_out <= '1'; end if; when one => if fsm_in = '0' then state_next <= zero; end if; end case; end processi