Assume the following latencies for the major functional units in processor design and ignore the delays of multiplexers

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Assume the following latencies for the major functional units in
processor design and ignore the delays of multiplexers and
wires.
Instr-Mem
Register read
ALU or Adder
Data-Mem
Register write
Latency
1.5 ns
0.5 ns
1 ns
1.5 ns
0.5 ns
a) What is the latency of the add instruction in the
single-cycle datapath?
b) What is the latency of the lw instruction in the single-cycle
datapath?
c)What is the latency of the beq instruction in this
single-cycle datapath?
d) If we only consider those types of
instructions add, lw and beq in the MIPS
ISA, what is the shortest clock cycle time for this single-cycle
processor