Implement the CPU shown in Figure 1 using Verilog, the CPU must be implemented using structural models only and should m

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Implement the CPU shown in Figure 1 using Verilog, the CPU must be implemented using structural models only and should m

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Implement The Cpu Shown In Figure 1 Using Verilog The Cpu Must Be Implemented Using Structural Models Only And Should M 1
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Implement the CPU shown in Figure 1 using Verilog, the CPU must be implemented using structural models only and should meet the following requirements: Register File Reg A Reg B Reg C Reg D Op1 Op2 Op3 Op4 Op1 Sel Op2 Sel N Operation 2 5 ah Op3 Sel Op4 Sel ALU N NY ILM Clk 2 Result Status Figure 1. CPU model • The CPU consists of an ALU, a register file, a clock, a status, and Result registers. • There is a 5-bit control line named Operation. Operation is responsible for selecting the operation to be performed by the ALU • The register file consists of four 8-bit registers (A, B, C, D). Assume values stored in the registers are unsigned.

The ALU has four 8-bit input Ports (Op1, Op2, Op3 and Op4). Op1, Op2, Op3 and Op4 values are fetched from the registers (A, B, C and D) based on Op1 Sel, Op2 Sel, Op3 Sel and Op4 Sel control lines as shown in Table 1. Table 1. Register Select Operand Selection Selected Register 00 01 C 10 11 The ALU has two output registers: result and status. Result is a 12-bit register while status is a 3- bit register. • At the negative edge of the clock, the ALU reads the selected registers and performs the required operation (By updating the result and the status registers). The operations being performed in the ALU are based on table 2. .

Operation Status Register affected bits Z 00000 00001 00010 00011 00100 00101 00110 00111 NE 01000 01001 Table 2. Operations in the ALU. ALU operation Result register NAND--Bitwise Operation (Op1&Op4) NOR--Bitwise Operation (Op1-|Op4) XOR -- Bitwise Operation (Opi Op4) Circular Shift Right for Op4 Op4 circular shifted Right Circular Shift Left for Op4 Op4 circular shifted Left One's complement for Op3 One's complement for Op3 Two's complement for Op3 Two's complement for Op3 Logical AND 1 if (Op1 != 0 AND Op2 !=0) O Otherwise Logical OR 1 if (Op1 != 0 OR Op2 = 0) 0 Otherwise Comparator O gif Op2 > Op4) 1 {if Op2 = Op4) 2 (if Op2 < Op4) Concatenate (Op4[2:0). Op2[2:01.0p3[1:01] Binary Addition Op1 +Op3 Binary Subtraction Opl - Op3 Binary to BCD Conversion-1 BCD representation of Op2 Ex: if Op2 = (1110 0011) Then result = (0010 0010 0111) sc Binary to BCD Conversion-2 BCD representation of Op3 Exif Op3 - (1110 001112 Then result = (0010 0010 0111) CD BCD Addition Covert the numbers in Op2 and Op3 to BCD then perform Op2 + Op3 01010 01011 01100 01101 Z Z, CV ZV 01110 01111 zc Z.C 10000 BCD Subtraction Ex: Op2 after conversion to BCD = (0011 0101) aco= 35 Op3 after conversion to BCD (0010 0110) aco=26 Result = (0000 0110 0001) eco=61 Covert the numbers in Op2 and Op3 to BCD then perform Op2 - Op3 Ex: Op2 after conversion to BCD = (0011 0101) eco 035 Op3 after conversion to BCD (0010 0110) co =26 ZV

The status register has three bits/flags. See Table 3. C = 1 when an addition operation produces carry, and O by default. Z = 1 when the result register equals to zero, and 0 by default. V= 1 when an addition or subtraction operation produces an overflow. Table 3. Status Register Bits Bit 2 Bit 1 Bit 0 с Z V
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