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It is required to design a synchronous sequential circuit that receives a serial input X that produces 1 when the input sequence is either {0111} or {1100} assuming no overlapping sequences. The output Z is also a bit stream that produces a 1 only after detecting any of the two sequences. Use an asynchronous reset input to reset the sequential circuit to its initial state. Example: 1 2 3 4 5 6 7 8 9 10 12 13 14 Clock cycle X Z 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0
c) (10 points) Write a structural Verilog model that models your implemented sequential circuit by modeling the D Flip-Flops and instantiating them and modeling the combinational part using either assign statement or gate primitives. d) (10 points) Write a behavioral Verilog description that models your state diagram in part (a). e) (10 points) Write a test bench that tests BOTH the structural Verilog model of part (c) and the behavioral Verilog model of part (d) using the example input sequence shown above. Call the outputs Z1 and Z2 for the models in (c) and (d), respectively. Start by resetting all flip-flops and then apply the input sequence of X. Verify that your circuit produces the correct output by including the generated waveform from simulation and comparing to the given example above.
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