- Rs Rt Rs Problem 4 Total Of 16 Marks The Fe22 Instruction Set Architecture Isa Is The Same As The Mt222 Isa Used Fo 1 (166.17 KiB) Viewed 99 times
- Rs Rt Rs Problem 4 Total Of 16 Marks The Fe22 Instruction Set Architecture Isa Is The Same As The Mt222 Isa Used Fo 2 (156.15 KiB) Viewed 99 times
CtrlG 2 CtrlF 15:12 Ctrle Control Ctrld 2:0 Ctrlc CtrlB Ctrla CLK CLK V WE3 =? CLK PC A RD 1-Mem 8:6 A1 RD1 11:9 ALU 00 01 10 A2 WE A RD D-Mem WD RD2 5:3 A3 WD3 R-File 15:6 «6 15:12 11:9 20 5:3 extend << 1 1 add PCNext Part a (6 marks). Fill in the following partial table of control signals. You must use X for don't care in any cell where the value of the control signal does not matter. instruction Ctrla CtrlB Ctric Ctrld Ctrle CtrlF CtrlG sub addi bea lui Part b (3 marks). For FE22 the C int type is 16-bit two's complement. Suppose that k is an int variable in $2. Write FE22 assembly language for the given C statement. You must use hexadecimal representation for immediate-mode operands. k = 0x579b;
Part c (3 marks). Suppose that the PC value is 0x4180 and that the word at instruction memory address 0x4180 is 0x1fdb. What value will the signal PCNext get? Answer in hexadecimal, and show how you got your answer. Part d (4 marks). Suppose that the circuit is to be run with a clock frequency of 0.5 GHz. Suppose also that are as given in the tables below. Find the maximum allowable tpd for the ALU. element tpd (ps) I-Mem 360 Control 160 R-File 200 2:1 mux 80 extend 70 =? 100 << 6 40 << 1 AND gate 50 ALU unknown adder 220 D-Mem 380 3:1 mux 140 element tsetup (ps) tpca (ps) PC 54 46 R-File 64 n/a D-Mem 82 n/a 40
Powers of Two n n n 0 1 2 3 4 5 6 7 2" 1 2 4 8 16 32 64 128 2n n 25 2n 8 256 16 65,536 24 16,777,216 9 512 17 131,072 25 33,554,432 10 1,024 18 262,144 26 67,108,864 11 2,048 19 524,288 | 27 134,217,728 12 4,09620 1,048,576 28 268,435,456 13 8,192 21 2,097,152 29 536,870,912 14 16,384 22 4,194,304 30 1,073,741,824 15 32,768 23 8,388,608 31 2,147,483,648 32 4,294,967,296 MIPS/MARS General Purpose Registers ON 0 $zero all bits are zero 1 $at assembler temporary 2 $v0 return value 3 $v1 return value 4 $a0 argument 5 $a1 argument 6 $a2 argument 7 $a3 argument 8 $t0 temporary 9 $t1 temporary 10 $t2 temporary 11 $t3 temporary 12 $t4 temporary 13 $t5 temporary 14 $t6 temporary 15 $t7 temporary 16 $50 local variable 17 $s1 local variable 18 $s2 local variable 19 $s3 local variable 20 $s4 local variable 21 $s5 | local variable 22 $s6 local variable 23 $s7 | local variable 24 $t8 temporary 25 $t9 temporary 26 $ko used by 0/S kernel 27 $k1 used by 0/S kernel 28 $gp global pointer 29 $sp stack pointer 30 $fp frame pointer 31 $ra return address 00
IEEE 754 floating-point formats The IEEE 754 single-precision (32-bit) floating-point format is as follows: Bit 31 is the sign bit. Bits 30-23 are the bits of the biased exponent. (The bias is 127, or 0x7f, or 0111 1111 in base two.) Bits 22-0 are the fraction bits. The IEEE 754 double-precision (64-bit) floating-point format is similar: Bit 63 is the sign bit. Bits 62–52 are the bits of the biased exponent. (The bias is 1023, or 0x3ff, or 011 1111 1111 in base two.) Bits 51-0 are the fraction bits. This table describes special interpretations for both single-precision and double-precision values: exponent bits fraction bits type of number all o all o zero all 0 not allo denormalized all 1 all o infinity all 1 not allo not a number Final Examination Instruction Subset Zero-extending a 16-bit constant means generating a 32-bit value by copying the 16-bit constant to bits 15-0 of the 32-bit value and making each of bits 31-16 equal to 0. Sign-extending a 16-bit constant means generating a 32-bit value by copying the 16-bit constant to bits 15-0 of the 32-bit value and making each of bits 31-16 equal to bit 15 of the 16-bit constant. Pseudoinstructions • la rdest, labelcopy address corresponding to label to register rdest. • li rdest, constant copy value of constant to register rdest. Instructions related to integer arithmetic with GPRS • add rdest, rsrc1, rsrc2-add register rsrc1 and register rsrc2; cause an exception on signed overflow, otherwise put result in register rdest. • addi rdest, rsrci, imm-add register rsrci and sign-extended constant imm; cause an exception on signed overflow, otherwise put result in register rdest. • addu rdest, rsrc1, rsrc2-add register rsrc1 and register rsrc2, put result in register rdest. • addiu rdest, rsrci, imm-add register rsrc1 and sign-extended constant imm, put result in register rdest. • sub rdest, rsrc1, rsrc2 subtract register rsrc2 from register rsrc1; cause an exception on signed overflow, otherwise put result in register rdest. • subu rdest, rsrc1, rsrc2 subtract register rsrc2 from register rsrc1, put result in register rdest. • slt rdest, rsrc1, rsrc2-put 1 in register rdest if register rsrc1 is less than rsrc2 using signed arith- metic, otherwise put 0 in register rdest. • slti rdest, rsrc1, imm-put 1 in register rdest if register rsrc1 is less than sign-extended constant imm using signed arithmetic, otherwise put ( in register rdest.
• sltu rdest, rsrc1, rsrc2 +put 1 in register rdest if register rsrc1 is less than rsrc2 using unsigned arithmetic, otherwise put 0 in register rdest. • sltiu rdest, rsrc1, imm-put 1 in register rdest if register rsrc1 is less than sign-extended constant imm using unsigned arithmetic, otherwise put 0 in register rdest. (Yes, it is somewhat weird that the constant gets sign-extended but the comparison treats numbers as unsigned.) • mult rsrc1, rsrc2-compute 64-bit signed product of signed integers from registers rsrc1 and rsrc2, put bits 63-32 in Hi register and bits 31–0 in Lo register. • multu rsrc1, rsrc2-compute 64-bit unsigned product of unsigned integers from registers rsrc1 and rsrc2, put bits 63–32 in Hi register and bits 31-0 in Lo register. • div rsrc1, rsrc2divide signed integer in rsrc1 by signed integer in rsrc2, put signed quotient in Lo register and signed remainder in Hi register. • divu rsrc1, rsrc2divide unsigned integer in rsrc1 by unsigned integer in rsrc2, put unsigned quotient in Lo register and unsigned remainder in Hi register. • mfhi rdest-copy word from Hi register to register rdest. • mflo rdest-copy word from Lo register to register rdest. Logical instructions involving GPRS • and rdest, rsrc1, rsrc2 do a bitwise AND of register rsrc1 and register rsrc2, put result in register rdest. • andi rdest, rsrci, imm -do a bitwise AND of register rsrc1 and zero-extended constant imm, put result in register rdest. • or rdest, rsrc1, rsrc2do a bitwise OR of register rsrc1 and register rsrc2, put result in register rdest. • ori rdest, rsrci, imm do a bitwise OR of register rsrc1 and zero-extended constant imm, put result in register rdest. • lui rdest, imm copy constant imm to bits 31-16 of register rdest, make bits 15-0 of rdest 0. • sll rdest, rsrc1, count shift value of register rsrc1 left by count bits, filling with O's from the right; put result in register rdest. • srl rdest, rsrc1, count shift value of register rsrc1 right by count bits, filling with O's from the left; put result in register rdest. Loads to and stores from GPRS • lw rdest, address -copy word from memory at address to register rdest. • sw rsrc, address copy word from register rsrc to memory at address. • lb rdest, address-copy byte from memory at address to bits 7-0 of register rdest, make each of bits 31-8 of rdest equal to bit 7 of that byte. .lbu rdest, address copy byte from memory at address to bits 7-0 of register rdest, make bits 31-8 of rdest equal to 0. • sb rsrc, address copy byte from bits 7-0 of register rsrc to memory at address.
Jump, branch, and conditional instructions All registers used in these instructions are GPRs. (But bc1t and bc1f do not access registers.) • j label-jump to instruction at label. • jal label-copy the address of the instruction following the jal instruction to $ra, and jump to the instruction at label. • jr reg jump to the instruction at the address in register reg. beq rsrc1, rsrc2, label -branch to instruction at label value of register rsrc1 equals value of register Isrc2. •bne rsrc1, rsrc2, label of register rsrc2. -branch to instruction at label if value of register rsrc1 does not equal value • bc1t label-branch to instruction at label if the coprocessor 1 flag is 1. • bc1f label -branch to instruction at label if the coprocessor 1 flag is 0. • movz rdest, rsrc1, rsrc2 copy register rsrc1 to register rdest, but only if register rsrc2 contains zero. • movn rdest, rsrc1, rsrc2-copy register rsrc1 to register rdest, but only if register rsrc2 does NOT contain zero. Instructions for crunching f-p numbers All operands are either 32-bit single-precision FPRs or 64-bit double-precision FPRs. . neg.s fdest, fsre put the negative of single-precision register fsrc into single-precision register fdest. • neg.d fdest, fsreput the negative of double-precision register fsrc into double-precision register fdest. • sqrt.s fdest, farc-compute the square root of single-precision register fsrc, put result in single- precision register fdest. • sqrt.d fdest, fsrc compute the square root of double-precision register fsrc, put result in double- precision register fdest. • add.s fdest, fsrc1, fsrc2-add single-precision registers fsrc1 and fsrc2, put result in single-precision register fdest. • add.d fdest, fsre1, fsrc2-add double-precision registers fsrc1 and fsrc2, put result in double-precision register fdest. • sub.s fdest, fsrc1, fsrc2 subtract single-precision register fsrc2 from single-precision register forc1, put result in single-precision register fdest. • sub.d fdest, fsrc1, fsrc2subtract double-precision register fsrc2 from double-precision register fsrc1, put result in double-precision register fdest. • mul.s fdest, fsrc1, fsrc2-multiply single-precision registers fsrc1 and fsrc2, put result in single- precision register fdest. • mul.d fdest, fsrc1, fsrc2 multiply double-precision registers fsrc1 and fsrc2, put result in double- precision register fdest. • div.s fdest, fsrc1, fsrc2divide single-precision register fsrc1 by single-precision register fsrc2, put result in single-precision register fdest. • div.d fdest, fsrc1, farce divide double-precision register farci by double-precision register fsrc2, put result in double-precision register fdest. • cvt.d.s fdest, fsrc-convert single-precision number from single-precision register fsrc to double- precision number, put result in double-precision register fdest
cut.d.w fdest, fsrc convert 32-bit signed integer from single-precision register fsrc to double-precision number, put result in double-precision register fdest • cvt.s.d fdest, fsrc-convert double-precision number from double-precision register forc to single- precision number, put result in single-precision register fdest cvt.s.w fdest, fare convert 32-bit signed integer from single-precision register forc to single-precision number, put result in single-precision register fdest • cvt.w.d fdest, fsrc-convert double-precision number from double-precision register forc to 32-bit signed integer, put result in single-precision register fdest • cvt.w.s fdest, fsrc-convert single-precision number from single-precision register fsrc to 32-bit signed integer, put result in single-precision register fdest nstructions for copying 32- or 64-bit patterns out of and/or into FPRs • mtc1 rsrc, fdest-copy 32-bit pattern from general purpose register rsrc to single-precision register fdest. • mfc1 rdest, førc copy 32-bit pattern from single-precision register fsrc to general purpose register rdest. mov.s fdest, fsrc-copy 32-bit pattern from single-precision register fsrc to single-precision register fdest. mov.d fdest, fsrc-copy 64-bit pattern from double-precision register fsrc to double-precision register fdest. • lwc1 fdest, address copy 32-bit pattern from memory word at address to single-precision register fdest. • ldc1 fdest, address copy 64-bit pattern from two memory words starting at address to double- precision register fdest. • swc1 fsre, address copy 32-bit pattern from single-precision register fsrc to memory word at address. • sdc1 fsre, address copy 64-bit pattern from double-precision register fsrc to two memory words starting at address. nstructions for comparing FPRs • c.l.s fsrc1, fsrc2 compare single-precision register fsrc1 with single-precision register fsrc2, make coprocessor 1 flag 1 if the comparison was true and 0 if the comparison was false (replace z with eq for equal to, 1t for less than, le for less than or equal to). • c.r.d fsrc1, fsrc2-compare double-precision register fsrc1 with double-precision register fsrc2, make coprocessor 1 flag 1 if the comparison was true and 0 if the comparison was false (replace r with eq for equal to, lt for less than, le for less than or equal to).
Machine-code formats for some MIPS instructions 0 R-type (add, sub, slt, and, or) ... 31 26 25 21 20 16 15 11 10 65 source source dest. 000000 00000 GPR 1 GPR 2 GPR "funct" field lw and sw (note that the offsets are in terms of bytes) ... 0 LW 31 26 25 21 20 16 15 pointer 100011 dest. GPR GPR offset 31 0 SW 26 25 21 20 16 15 101011 pointer source GPR GPR offset 0 beq (note that the offset is an instruction count) ... 31 26 25 21 20 16 15 source source 000100 offset GPR 1 GPR 2 j... 31 26 25 0 000010 bits 27-2 of jump target address Information about some microarchitectures from Chapter 7 of the course textbook ALU specification for computers of textbook Chapter 7 ALUControl 3 32 HA Zero + ALU Result 32 32 HB ALUControl ALUResult 000 bitwise AND of A and B 001 bitwise OR of A and B 010 32-bit sum of A and B 110 32-bit subtraction result for A-B 111 SLT result for signed comparison A<B The 1-bit signal called Zero is 1 if all 32 bits of ALUResult are 0, and is 0 if one or more bits of ALUResult are 1.
Textbook Figure 7.11 Below is Figure 7.11 from Harris and Harris, Digital Design and Computer Architecture, 2nd edition, copy- right © 2013, Elsevier Inc. This is a "single-cycle” implementation of the Chapter 7 MIPS instruction subset. PCSrc Memto Reg Control MemWrite Unit Branch ALUControl2:0 31:26 Op ALUSrc Funct RegDst RegWrite 5:0 CLK CLK 25:21 WE3 Srca Instr RD1 A1 CLK PC PC A RD Instruction Memory Zero ALUResult ALU 20:16 0 SrcB A2 RD2 A3 WD3 Register File WE ReadData A RD Data Memory WD WriteData 20:16 15:11 WriteReg4.0 PCPlus4 SignImm 1500 <<2 Sign Extend PCBranch Result
Textbook Figure 7.47 Below is Figure 7.47 from Harris and Harris, Digital Design and Computer Architecture, 2nd edition, copy- right © 2013, Elsevier Inc. This circuit attempts to implement the Chapter 7 MIPS instruction subset with a five-stage pipeline. It can process many instruction sequences correctly, but will not properly handle sequences with data hazards or control hazards. CLK CLK CLK Control Unit RegWriteW MemtoRegw Reg WriteD MemtoRegD MemWrite BranchD ALUControl ALUSD RegDstD RegWrite E MemtoRegE Mem WriteE Branche ALUControlE20 ALUSIE RegDate RegWriteM MertoRegM MemWriteM BranchM HPCSM 31:26 Op 5:0 Funct ALUOW CLK CLK CLK CLK 25-21 WE3 SrcAE ZeroM WE PC PCF Instr A1 RD1 RD ALUOutM ReadDataW A Instruction Memory 20:16 ALU SrcBE A2 RD2 A3 Register WD3 File A RD Data Memory WD Write Data WriteDataM 20:16 RtE WriteRegE. Write RegM WriteRegW40 15:11 RdE 15:0 <<2 Sign Extend SignImmE PCBranch PCPlus F PCPlus4D PCPlus4E Result
Textbook Figure 7.47 Below is Figure 7.47 from Harris and Harris, Digital Design and Computer Architecture, 2nd edition, copy- right © 2013, Elsevier Inc. This circuit attempts to implement the Chapter 7 MIPS instruction subset with a five-stage pipeline. It can process many instruction sequences correctly, but will not properly handle sequences with data hazards or control hazards. CLK CLK CLK Control Unit RegWriteW MemtoRegw Reg WriteD MemtoRegD MemWrite BranchD ALUControl ALUSD RegDstD RegWrite E MemtoRegE Mem WriteE Branche ALUControlE20 ALUSIE RegDate RegWriteM MertoRegM MemWriteM BranchM HPCSM 31:26 Op 5:0 Funct ALUOW CLK CLK CLK CLK 25-21 WE3 SrcAE ZeroM WE PC PCF Instr A1 RD1 RD ALUOutM ReadDataW A Instruction Memory 20:16 ALU SrcBE A2 RD2 A3 Register WD3 File A RD Data Memory WD Write Data WriteDataM 20:16 RtE WriteRegE. Write RegM WriteRegW40 15:11 RdE 15:0 <<2 Sign Extend SignImmE PCBranch PCPlus F PCPlus4D PCPlus4E Result