Question 2: For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access
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Question 2: For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access
Question 2: For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Offset 5-0 Index 10-6 Tag 31-11 a b. What is the cache block size (in words)? How many entries does the cache have? What is the ratio between total bits required for such a cache implementation over the data storage bits? C