Design An N Bit Alu Unit Set The Default Value In Your Generic Statement For Input A And B To 16 Using Vhdl That Imple 1 (46.5 KiB) Viewed 35 times
Design An N Bit Alu Unit Set The Default Value In Your Generic Statement For Input A And B To 16 Using Vhdl That Imple 2 (20.72 KiB) Viewed 35 times
Design an N bit ALU unit (set the default value in your generic statement for input A and B to 16) using VHDL that implements the following operations: 1. Arithmetic Addition: Output_of_ALU = A + B; 2. Arithmetic Subtraction: Output_of_ALU = A - B; 3. Arithmetic Multiplication: Output_of_ALU = A*B; 4. Arithmetic Division: Output_of_ALU = A/B; 5. Logical Shift Left: Output_of_ALU = A logical shifted left by 1; 6. Logical Shift Right: Output_of_ALU = A logical shifted right by 1; 7. Rotate Left: Output_of_ALU = A rotated left by 1; 8. Rotate Right: Output_of_ALU = A rotated right by 1; 9. Logical AND Output_of_ALU = A AND B; 10. Logical OR: Output_of_ALU = A OR B; 11. Logical XOR: Output_of_ALU = A XOR B; 12. Logical NOR: Output_of_ALU = A NOR B; 13. Logical NAND: Output_of_ALU = A NAND B; 14. Logical XNOR: Output_of_ALU = AXNOR B; 15. Greater comparison: Output_of_ALU = 1 if A > B else 0; 16. Equal comparison: Output_of_ALU = 1 A = B else 0;
Hints: • Use a case statement to select the operation • Use a STD_LOGIC_VECTOR input associated with the numbers listed above as your case selection signal o i.e. for 1. Arithmetic Addition use "0000" and "1111" for 16. Equal comparison use • Submit the code in a .txt file or a .vhd file, submit the screenshot of Vivado synthesis as well • The submission must pass the Vivado synthesis • Explain the logic in no more than one page
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