(15 points) In this problem you are asked to design a CMOS static logic to implement the function Z=A+B(C+D). (a) Draw t

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15 Points In This Problem You Are Asked To Design A Cmos Static Logic To Implement The Function Z A B C D A Draw T 1 (78.58 KiB) Viewed 62 times

(15 points) In this problem you are asked to design a CMOS static logic to implement the function Z=A+B(C+D). (a) Draw the circuit schematic of the gate. (b) Size all the transistors such that the worst-case delay becomes identical to a standard 1X inverter (1X NMOS and 2X PMOS). (c) Which input vector (ABCD) gives the best case high-to-low propagation delay, TPHL (d) Determine the effective pull-down transistor size for the input vector in part c. (e) Which input vector (ABCD) gives the best case low-to-high propagation delay, TPLH (f) Determine the effective pull up transistor size for the input vector in part e.