3. (20 points) In the following circuit, modules A, B, C and D are combinational circuits, with the delay of each module

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3 20 Points In The Following Circuit Modules A B C And D Are Combinational Circuits With The Delay Of Each Module 1 (124.03 KiB) Viewed 44 times

3. (20 points) In the following circuit, modules A, B, C and D are combinational circuits, with the delay of each module showing in the figure. Assume wire and registers have no delay. a) The registers have Clock-to-Q delay 2ns, setup time requirement is 8 ns, and hold time is 10 ns. What is the fastest clock rate to avoid setup time violations? Is there any hold time violation? b) Use pipeline to maximize the performance of the circuit. What is your throughout and latency? Is there any hold time violation? Register12 Module 15ths ModuleBE 20ths? ModuleCE 257hs? Moduled 10ns? Register23