Write a Stopwatch Verilog program for DE10 standard FPGA. use all the 6 Segment displays to show the Stopwatch time and

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Write a Stopwatch Verilog program for DE10 standard FPGA.
use all the 6 Segment displays to show the Stopwatch time and
record
During the run:
a. If you press Start/Stop, the timer pauses, then:
 If you press Start/Stop button again, the timer resumes.
 If you press Lap/Reset button, the timer resets to 00:00
b. If you press Lap/Reset button, the lap time is recorded and
displayed on the other 4 digits. We will
record only one lap time, so the previous lap time recorded if any
will be erased. The timer still
runs and displays on the first 4 digits.
 You need to derive a state diagram from the above
description.
 You must design the system using Finite State Machine approach in
SystemVerilog