sequential circuit with 400-MHz clock frequency and VDD = 1V. The
delay of each NOR gate is 1/8 of the clock cycle. The input
waveforms are shown below.
A. Draw the waveforms at node A, B, C and F. Remember to take
any glitches into account.
B. For each node (X, Y, A, B, C, F), calculate the
activity factor α across the first 4 cycles. Note that you
can estimate α by diving the number of transitions at a node
(during the first 4 cycles) by the number of clock transitions for
the same period (which is 8)
C. For each node (X, Y, A, B, C, F), calculate the
average switching power dissipation. What is the total
average switching power dissipation for the entire circuit?
- The Following Combinational Logic Block Operates Inside A Larger Sequential Circuit With 400 Mhz Clock Frequency And Vdd 1 (75.3 KiB) Viewed 50 times