For A:
Choice 1 of 3:a 1-to-2 Decoder with the '0' output connected to
the top register, and the '1' output connected to the bottom
one.
Choice 2 of 3:a 1-to-2 Demux with the '0' output connected to
the top register, and the '1' output connected to the bottom one;
The S input connects to the demux' selector bit, and the demux
input is '1'.
Choice 3 of 3:an inverter for the top register and a direct
connection for the lower one.
For B:
Choice 1 of 3:an OR gate
Choice 2 of 3:a 4x 2-to-1 encoders for each output bit.
Choice 3 of 3:a 2-to-1 mux, with the S input connected to the
mux' selector bit.
Build a 2x 4-bit register file with the input D[3:0], S and the output Q[3:0], using any number of 4 bit registers below. (Note 1: when EN is 1, the register updates the value. When EN is 0, the register holds the value. Note 2: when S is O the upper register is selected, and when S is 1, the lower register becomes active.) D[3:0) D[3:0) Q[3:0] 4-bit Register EN B -Q[3:0) S А D[3:0) Q[3:0) 4-bit Register EN Select ALL possible logic circuits for A and B that can form a 2x 4-bit register file.
Build a 2x 4-bit register file with the input D[3:0], S and the output Q[3:0], using any number of 4 bit registers below
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answerhappygod
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Build a 2x 4-bit register file with the input D[3:0], S and the output Q[3:0], using any number of 4 bit registers below
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