- 2 20 Pts A Sequence Detector Is To Be Designed To Detect Both The Sequence 0101 And 1011 Simultaneously You Will Dev 1 (153.24 KiB) Viewed 56 times
2. [20 pts] A sequence detector is to be designed to detect both the sequence 0101 and 1011 simultaneously. You will develop a state diagram with one input variable X and one output variable Z. The output is 1 if and only if the last four input bits are either 1011 or 0101. Note that sequences may overlap. Sample input: 0010101101101101010 Sample output: 0000101100100100010 A) [8 pts] Draw the state diagram. Label each arc with X/Z. Label the initial state with So and other states with Si, S2, S3, etc. Use a minimum number of states. Please use Mealy model. You can draw the state diagram on a white paper, and then, take a photo of it. Next, you can insert the photo here. Hint: you only need to use 7 states. Start So
B) = [4 pts] Implement this state diagram using the minimum number of D flip- flops. Complete the following state table for this state diagram. Assume that we use the following state assignments: So = 000, S1 = 001, S2 =010, S3 = 011, S4= 100, S5 = 101, S6 = 110, S7 = 111. Note that you might not need all of the 8 states. Please use don't cares conditions for unused states. Q2 Q1 Q. X Q2 (t+1) Q1 (t+1) Q. (t+1) Z = =
[4 pts] Complete the following four K maps using the K-map template below. And then derive optimized Boolean expressions for the inputs to the D flip-flops and the output of the sequential circuit. Note that D2 stands for Q2(t+1). Similarly, D1 stands for Q1(t+1) and Do stands for Qo(t+1). Q0 Q1 Q2 D2: D: Do: Z: D2= D1= Do= Z= D) [4 pts] Draw the logic diagram of the circuit. Q2 D с R O 101 D C R lo D R