Question 4. Consider a main memory constructed with Synchronous DRAM chips that have the following timing requirements:

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Question 4. Consider a main memory constructed
with Synchronous DRAM chips that have the following timing
requirements: 1 bus cycle to transfer the address, 10 bus cycles
access latency, and 1 bus cycle to transfer a word. Assume that
32-bits of data can be transferred in parallel. If a 200-MHz clock
is used for the bus and memory, and burst mode is used to transfer
a block, how long does it take to access and transfer 32 bytes of
data, 64 bytes of data, and 128 bytes of data?
Solution: