- Simulate In Modelsim And Synthesize In Synplifypro 1 (30.17 KiB) Viewed 45 times
SystemVerilog module sillyfunction(input logic a, b, c, output logic y); assign y=~a &~b &~C | a &~b &~C1 b ~ a & ~b & C; endmodule
simulate in ModelSim and synthesize in SynplifyPro
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simulate in ModelSim and synthesize in SynplifyPro
simulate in ModelSim and synthesize in SynplifyPro
SystemVerilog module sillyfunction(input logic a, b, c, output logic y); assign y=~a &~b &~C | a &~b &~C1 b ~ a & ~b & C; endmodule
SystemVerilog module sillyfunction(input logic a, b, c, output logic y); assign y=~a &~b &~C | a &~b &~C1 b ~ a & ~b & C; endmodule
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