ZELLE 1919 POK TOP VIEW W PACKAGE ACLAREN Ο νες 10 200 VOLK 20 LE 7474 CLK 10 10 GND TU 7474 7476 Pek 1 Clock 1 Preset 1

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ZELLE 1919 POK TOP VIEW W PACKAGE ACLAREN Ο νες 10 200 VOLK 20 LE 7474 CLK 10 10 GND TU 7474 7476 Pek 1 Clock 1 Preset 1 Clear 1 VB 2 Clock 2 Preset 2 Clear K 10 10 Ground 132 129 1020 021 uooou CER 3. Experiments using Shift Registers You will first investigate the operation of shift registers. As shown in Fig. 1, a basic shift register comprises a chain of flip-flops arranged to transfer data from the serial input to the serial output SI SO Serial input Serial output Pa PC CEK Fig. 1. Diagram of a basic shift register Features of advanced shift registers may include a clear input, a shift/don't shift control, bidirectional shifting, and a parallel load capability. The 74195 shift register I used in this tab is 24-bit shift register with parallel load and asynchronous clear. The pin assignments to the inputs and outputs are shown in Fig. 2. The single control line Inbeled SH/LD (shiftload) determines the synchronous operation of the register. When SHLD-0, the control input is in the load mode and the four data inputs are transferred into the internal flip-flops, QA through OD. When SHLD-1, the control input is in the shift mode and the information in the register is shifted right from QA toward OD. The serial input into QA during the shift is determined from the J and K inputs. The 2 inputs behave like the and the complement of K of a K flip-flop. If I and Kare connected together, the combined input will act like the input of a D-type flip-flop
Shit carload Clock 1 10 X X V Function table Serial R input Function X x Asynchronx clear x * No change in output x Load input data 0 0 Shifrom A toward 0.040 1 1 Shift from QA toward OD QA = 1 1 Clear CLK 1 1 1 X X x O 1 0 1 1 1 10 Clock CK 1 1 15 Shift/load SHILD 2 14 Serial inputs 3 13 Data outputs R. QA QB OC OD QD 74195 2 4 12 A 5 11 B Complement of OD Data inputs 7 D GND Fig. 2. Pinout and function table of 74195 shift register IC. 1. Verify function table: The function table for the 74195 shows the mode of operation of the register. When the clear input goes to 0, the four flip-flops clear to 0 asynchronously. (1.c., without waiting for the clock). Synchronous operations are triggered by a positive transition of the clock. When SH/LD is set to 0, a clock pulse triggers a parallel load of the data inputs A, B, C, D. When SH/LD is set to 1, bits are transferred to the right, according to: serial INA, A™B, B+C, C+D, D serial OUT. As noted above, the J and K inputs must be connected together to form the serial input. Perform some experiments using the following table that will verify the operation of the 74195 IC. Show that it performs all the operations listed in the function table. Record the numbers you get for each shift in the following table. Clockl Clock2 Clock3 Clock4 Clocks Clocko Clock7 Clocks Initial value loaded(QOQ QuQA) 0000 with serial input 1 0110 with serial input 0101 with serial input 1111 with serial input 0 6
2. Ring Counter: a ring counter is a circular shift register with the signal from the serial output Qo going into the serial input. Connect the J and K input together to form the serial input. Use the load condition to preset the ring counter to an initial value of 0001. Rotate the single bit with the shift condition and check the state of the register after each clock pulse. Initial value Clocki Clock2 Clock3 Clock4 Clocks Clock. Clock7 Clock8 loaded(QuQCQUQA) 0001 (b) A switch-tail ring counter uses the complement output of Qo for the serial input. Present the switch-tail ring counter to 0000 and predict the sequence of states that will result from shifting. Verify your prediction by observing the state sequence after each shift. Initial value Clockl Clock2 Clock3 Clock4 Clocks Clock6 Clock7 Clock8 loaded(QOQCQ QA) 0000 3. Feedback shift register: A feedback shift register is a shift register whose serial input is connected to some function of selected register outputs, such as the one shown in Fig. 3. 1 11 1314 16 DODO Fig. 3. A 16-bit feedback shift register configured to generate a maximal-length sequence of 65535 bits. Connect a feedback shift register whose serial input is the exclusive-OR of outputs QC and QD. Predict the sequence of states of the register, starting from state 0001. Verify your prediction by observing the state sequence after each clock pulse. Clockl Clock2 Clock3 Clock4 Clocks Clock6 Clock7 Clock8 Initial value loaded(QuQCQ&QA) 0001 One important application of feedback shift registers is to generate maximal-length sequences, also called pseudo-random bit sequences (PRBSs). Due to their special mathematical properties, these sequences are widely used to test digital communications systems and also to generate pseudorandom numbers. To convert your shift register into a random number generator, start by creating a gated clock Connect the TTL output of the function generator, set at -50 Hz, to one input of an AND gate, connect a logic switch to the other input, and connect the output of the AND gate to the CLK input of the 74195. While the logic switch (now a Shift Don't Shift control) is in the HI state, the shift register will run rapidly through its pseudorandom sequence of states, causing the indicators to flicker. When the switch is moved to the LO state, a (pseudo) random number between 1 and 15 will appear on the indicators Demonstrate to instructor after completion 7
ICs needed: 7474 (D-FF), 3x 7476(JK-FF), 74195 (shift register), 7486(XOR), 7404 (inverter), 2x 7408 (AND), 7432 (OR)