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Rd .tran 2m ;.ac dec 100 1E-1 159 .param vth 1.5 Сс HE 10u VDD M1 R1 in M BS170 18 47k RL 1 Meg Vsig SINE(6 0.01 10k) AC
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Rd .tran 2m ;.ac dec 100 1E-1 159 .param vth 1.5 Сс HE 10u VDD M1 R1 in M BS170 18 47k RL 1 Meg Vsig SINE(6 0.01 10k) AC
Rd .tran 2m ;.ac dec 100 1E-1 159 .param vth 1.5 Сс HE 10u VDD M1 R1 in M BS170 18 47k RL 1 Meg Vsig SINE(6 0.01 10k) AC 10 Rs Cs 1100u Design the bias circuit above by choosing Rd and Rs such that VRd = VRs = 7 V. In this case KVL then tells us that VDS = 18 - VRd - VRs = 4 V = = =
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