Design a lag compensator for the system shown below such that the steady-state error of the compensated system for a ram
Posted: Fri Apr 29, 2022 10:34 am
Design a lag compensator for the system shown below such that the steady-state error of the compensated system for a ramp input is reduced by a factor of 20 while maintaining a 15% overshoot for a step input. For the lag compensator, select the pole at s = -0.01 and 1 the zero at s = -0.2. Note: G(S) Use Matlab, as needed. s(s+7) Gain Plant R(S) C(s) K G(s)