37. If you decrease the frequency of a digital circuit which of the following are true? (a) increase TPDMIN (b) all answ
Posted: Fri Apr 29, 2022 9:14 am
37. If you decrease the frequency of a digital circuit which of the following are true? (a) increase TPDMIN (b) all answers are correct (c) reduce the power consumption (d) decrease TPDMAX 38. For digital CMOS circuits the worst case delay can be determined by knowing? (a) the transistor lengths, load capacitance and supply voltage (b) the transistor mobilities, load capacitance and supply voltage (c) the transistors widths, load capacitance and supply voltage (d) the transistor currents, load capacitance and supply voltage 39. In a state of the art digital ASIC, what percentage of the power would typically be consumed by the clock tree? (a) 60-70% (b) 1-10% (c) 40-50% (d) 85-95%