18. How many errors does the following verilog module code have? module something (a,b,c,d); input b,c,d; output [7:0] a

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18 How Many Errors Does The Following Verilog Module Code Have Module Something A B C D Input B C D Output 7 0 A 1 (1.71 MiB) Viewed 21 times

18. How many errors does the following verilog module code have? module something (a,b,c,d); input b,c,d; output [7:0] a; reg (7:0) a; always @ (posedge c or negedge d) begin if (!d) begin a <= 8'b00000000; end else if (b) begin a <= a + 2; end else begin a <= a; end end endmodule (b) 2 (c) 0 (d) 1 19. We prefer to use an FPGAs instead of an ASICs when: (a) 3 (a) required power consumption is high (b) all answers are correct (c) sales volumes are high (d) required operating frequency is high