16. How many errors does the following verilog module code have? module something (a,b,c,d); input b,c,d output [] az re

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16. How many errors does the following verilog module code have?
module something (a,b,c,d); input b,c,d
output [] az
reg (1) ar
always (posedge cor negedge d) begin
if (d) begin a 500000000;
end else if (b) begin
a <= a + 21
and else begin a o az
and
end
endmodule
(a) 1
(b) 0
(c) 2
(d) 3
17. We prefer to use an FPGAs instead of an ASICS when:
(a) sales volumes are high
(b) required power consumption is high (e) required operating frequency is high
(d) all answers are correct
18. In a state of the art digital ASIC, what percentage of the power would typically be consumed by
the clock tree?
(a) 60-70% (b) 1-10%
(e) 40-50%
(d) 85-90%
please solve this with in 30 minutes
please solve all parts of question