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11. Upon synthesis, will a variable declared as a reg in an always@(clk) procedure generate flip-flops? (a) yes, if ther
Posted: Fri Apr 29, 2022 9:08 am
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- 11 Upon Synthesis Will A Variable Declared As A Reg In An Always Clk Procedure Generate Flip Flops A Yes If Ther 1 (111.91 KiB) Viewed 25 times
11. Upon synthesis, will a variable declared as a reg in an always@(clk) procedure generate flip-flops? (a) yes, if there is no reset signal (b) no (c) maybe (d) yes, always 12. What is common name for the circuit implemented by the following verilog code? module something (a,b,c,d,e); input b, c, d, e; output [7:0] a; reg (7:0) a; always @ (posedge b or posedge c) begin if (c) begin a <= 8'do ; end else if (d) begin a <= a + 1; end else if (e) begin a <= a - 1; end else begin a <= a; end end endmodule (a) one hot counter (b) BCD counter (c) gray code counter (d) up/down counter