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17. If a D flip-flop has a negative hold time which of the following statements are true? (a) all answers are correct (b) if the d input changes after the setup time the output will be synchronous (c) if the d input changes at the clock edge the output will be synchronous (d) any circuits using these flip-flops cannot have hold time violations 18. An asynchronous signal that is synchronized by a D flip-flop and goes temporarily metastable has less of a chance of causing a problem if: (a) the hold time of the D flip-flop is increased (b) the asynchronous signal changes infrequently (c) the synchronizing clock is high frequency (d) the setup time of the D flip-flop is increased