Answer Happy

3. Why is it important to put a default in a case statement even if all cases are defined? (a) prevents hold time violations (b) minimizes the logic (c) prevents future errors (d) prevents unwanted latches 4. How many errors does the following verilog module code have? module something input a input b. input c, output reg d ): always e (posedge a) begin if (c) begin de l'10: end else begin d = b; and end andmodule (c) 2 (d) 3 (b) 1 5. System Verilogies random testing to: () allows you to verify the design sequentially (b) simplify the verification environment (c) increase simulation accuracy (d) speed up the verification process