37. An asynchronous signal that is synchronized by a D flip-flop and goes temporarily metastable has les of a chance of

[answerhappygod]

37. An asynchronous signal that is synchronized by a D flip-flop and goes temporarily metastable has les of a chance of causing a problem if
(a) the setup time of the D flip-flop is increased (b) the synchronizing clock is high frequency
(e) the asynchronous signal changes infrequently (d) the hold time of the D flip-flop is increased
38. For digital CMOS circuits the worst case delay can be determined by knowing!
(a) the transistor currents, load capacitance and supply voltage. (b) the transistors widths, load capacitance and supply voltage
(c) the transistor lengths, load capacitance and supply voltage (d) the transistor mobilities, load capacitance and supply voltage.
40. Why are errors with asynchronous inputs to synchronous circuits difficult to debug?
(a) they typically correct themselves
(b) they typically don't cause a system failure
(c) they typicaly happen infrequently (d) they typically involve multiple signale
please solve this in 30 minuts