34. What is a disadvantage when asynchronously resetting a counter that uses flip-flops with synchronous resets (a) all

[answerhappygod]

34.
What is a disadvantage when asynchronously resetting a counter that uses flip-flops with synchronous resets
(a) all answers are correct. (b) may have temporary false count
(e) may never ret
(d) requires extra hardware in the flip-flops
35. An advantage of dynamic D latches vs. clocked inverter D latches is
(a) all answers are correct (b) higher noise margins
(c) fewer transistors
(d) higher minimum operating frequency
36. Upon synthesis, will a variable declared as a reg in an always (elk) procedure generate Hip-flops?
(a) yes, if there is no reset signal
(b) no
(c) yes, always
(d) maybe
please solve with in 30 minutes.