What is common name for the circuit implemented by the following verilog code? module something (a,b,c,d,e, f); input b,
Posted: Fri Apr 29, 2022 9:01 am
What is common name for the circuit implemented by the following verilog code? module something (a,b,c,d,e, f); input b, c, d, e, f; output 17:0] a; reg (7:0) a; always @ (posedge b) begin if (c) begin a <= 8'd ; and else if (d) begin case (e) 0: a <= {a[6:0), f): 1: a <= {f, a(7:11); endcase and else begin a <a end end endmodule (a) parallel in serial out register (b) linear feedback shift register (c) priority shift register (d) bidirectional shift register