The situation: Your program is in the middle of iterating through a giant array, adding a constant to each value. In oth

[answerhappygod]

The situation: Your program is in the middle of iterating
through a giant array, adding a constant to each value. In other
words: load-add-store, over and over. (Assume this will continue
throughout the DMA transfer.) The instruction stream is getting a
100% hit rate in the instruction cache, but all of the references
to the array elements have to access the memory. The processor is
not pipelined. It does have a standard five-stage execution
(Fetch-Decode-Execute-Memory-Writeback) with each stage taking one
bus cycle.
The DMAC is then ready to transfer 8 bytes from the host memory
to an I/O device. It is currently using transparent mode. Assuming
the DMAC gets every bus cycle not used by the
CPU, it will take ___________ cycles to complete the transfer.