Answer Happy

a) (5 pts) You are given a logic function to implement: Out = (AB + CD EF. Draw a schematic (with NMOS and PMOS transistors) of a static CMOS circuit that implements the logic. Limit fan-in for a logic gate to 3. How many stages (gates) do you need? Size each gate to match the unit-sized inverter in the worst case. There may be more than one correct answer. b) (8 pts) For the circuit you designed for part a), find the input switch pattern that causes the longest output transition delay (the worst between tplh and tpHL) and calculate the actual delay. State any assumptions you need to make to obtain a numerical value for the delay time.
c) (7 pts) Draw a schematic with NMOS and PMOS transistors of a dynamic domino logic circuit that implements Out. Note that, for a domino logic, you should rewrite the original function to an equivalent logic (each stage needs to be non-inverting). List any advantages you see of this approach.