Design a differential input, single-ended output operational amplifier which has a resistive feedback network to achieve
Posted: Fri Apr 29, 2022 8:52 am
Design a differential
input, single-ended output operational amplifier which has a
resistive feedback network to achieve the desired closed loop
gain.
The suggested
resistor value between the output and inverting input is 10kΩ. The
resistor between the inverting input and ground sets the
closed-loop gain.
The amplifier
current bias reference is generated externally. The amplifier must
meet the following performance criteria:
Semiconductor process geometry
0.6µm
Minimum closed-loop gain
6dB
Dual power supply
Vdd = +15V; Vss = -15V
Maximum quiescent power dissipation
50mW
External bias current
50µA
Minimum output current (source and
sink)
5mA
Minimum Slew rate
15 V/µs
Input bias current
< 10µA
Minimum positive output voltage
swing
+13.5V
Maximum negative output voltage
swing
-13.5V
Maximum capacitance load
50pF
Minimum resistive load
3kΩ
Minimum open loop gain
100dB (100,000)
Minimum phase margin
45deg
Minimum gain margin
6dB
Minimum closed-loop bandwidth, (Cload
=
10pF, Rload = 5kΩ)
5MHz
The amplifier must use bipolar and MOS
transistors.
1. Complete electrical schematic showing transistor dimensions
(can be added
as Spice directive > Comment).
2. An output file in LTSpice “.asc” or a SPICE netlist which
includes simulation
benches (.ac, .dc. .step statements)
3. Draw an equivalent small signal circuit of the entire
amplifier.
4. First approximation calculations using formula for
the
following parameters: open-loop gain, open-loop bandwidth and
common
mode rejection.
5. Spice simulation plots indicating that the following
parameters have been
met.
1. Open loop gain
2. Closed loop bandwidth
3. Bode plots for 5 different capacitive loads up to the maximum
specified capacitive
load showing phase and gain margin.
4. Output voltage swing across the minimum resistive load for a
differential voltage
source freq = 1Hz (shows dc performance)
6. Table with performance specifications based on calculations
and/or
simulations.
input, single-ended output operational amplifier which has a
resistive feedback network to achieve the desired closed loop
gain.
The suggested
resistor value between the output and inverting input is 10kΩ. The
resistor between the inverting input and ground sets the
closed-loop gain.
The amplifier
current bias reference is generated externally. The amplifier must
meet the following performance criteria:
Semiconductor process geometry
0.6µm
Minimum closed-loop gain
6dB
Dual power supply
Vdd = +15V; Vss = -15V
Maximum quiescent power dissipation
50mW
External bias current
50µA
Minimum output current (source and
sink)
5mA
Minimum Slew rate
15 V/µs
Input bias current
< 10µA
Minimum positive output voltage
swing
+13.5V
Maximum negative output voltage
swing
-13.5V
Maximum capacitance load
50pF
Minimum resistive load
3kΩ
Minimum open loop gain
100dB (100,000)
Minimum phase margin
45deg
Minimum gain margin
6dB
Minimum closed-loop bandwidth, (Cload
=
10pF, Rload = 5kΩ)
5MHz
The amplifier must use bipolar and MOS
transistors.
1. Complete electrical schematic showing transistor dimensions
(can be added
as Spice directive > Comment).
2. An output file in LTSpice “.asc” or a SPICE netlist which
includes simulation
benches (.ac, .dc. .step statements)
3. Draw an equivalent small signal circuit of the entire
amplifier.
4. First approximation calculations using formula for
the
following parameters: open-loop gain, open-loop bandwidth and
common
mode rejection.
5. Spice simulation plots indicating that the following
parameters have been
met.
1. Open loop gain
2. Closed loop bandwidth
3. Bode plots for 5 different capacitive loads up to the maximum
specified capacitive
load showing phase and gain margin.
4. Output voltage swing across the minimum resistive load for a
differential voltage
source freq = 1Hz (shows dc performance)
6. Table with performance specifications based on calculations
and/or
simulations.